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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
PD4483362
8M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 256K-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE
Description
The PD4483362 is a 262,144 words by 36 bits synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The PD4483362 is suitable for applications which require synchronous operation, high-speed, low voltage, highdensity memory and wide bit configuration, such as cache and buffer memory. The PD4483362 is packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness for high density and low capacitive loading.
Features
* Fully synchronous operation * HSTL Input / Output levels * Fast clock access time : 3.8 ns (133 MHz) * Asynchronous output enable control : /G * Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9) * Common I/O using three-state outputs * Internally self-timed write cycle * Late write with 1 dead cycle between Read-Write * 3.3 V (Chip) / 1.5 V (I/O) supply * 100-pin PLASTIC LQFP package, 14 mm x 20 mm * Sleep Mode : ZZ (Enables sleep mode, active high)
Ordering Information
Part number Access time 3.8 ns Clock frequency 133 MHz Package 100-pin PLASTIC LQFP (14 x 20)
PD4483362GF-A75
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. M14440EJ1V0DS00 (1st edition) Date Published April 2001 NS CP(K) Printed in Japan
(c)
2001
PD4483362
Pin Configuration (Marking Side)
/xxx indicates active low signal.
100-pin PLASTIC LQFP (14 x 20) [ PD4483362GF ]
SA17 /SBd /SBb /SBa VREF /SBc SA6 SA7 SA8 SA9 /SW VDD VSS
/SS
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQc9 DQc8 DQc7 VDDQ VSSQ DQc6 DQc5 DQc4 DQc3 VSSQ VDDQ DQc2 DQc1 NC VDD NC VSS DQd1 DQd2 VDDQ VSSQ DQd3 DQd4 DQd5 DQd6 VSSQ VDDQ DQd7 DQd8 DQd9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQb9 DQb8 DQb7 VDDQ VSSQ DQb6 DQb5 DQb4 DQb3 VSSQ VDDQ DQb2 DQb1 VSS NC VDD ZZ DQa1 DQa2 VDDQ VSSQ DQa3 DQa4 DQa5 DQa6 VSSQ VDDQ DQa7 DQa8 DQa9
SA5
SA4
SA3
SA2
SA1
SA0
NC
VREF
VDD
VREF
NC
VSS
NC
SA10
SA11
SA12
SA13
NC
/G
/K
K
SA14
SA15
Remark Refer to Package Drawing for 1-pin index mark. 2
Preliminary Data Sheet M14440EJ1V0DS
SA16
PD4483362
Pin Name and Functions
Pin name SA0 to SA17 Pin No. Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input 45, 46, 47, 48, 49, 50, 83
DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9 /SS /SW /SBa Note1 /SBb /SBc /SBd /G ZZ
Note2 Note1 Note1 Note1
63, 62, 59, 58, 57, 56, 53, 52, 51 68, 69, 72, 73, 74, 75, 78, 79, 80 13, 12, 9, 8, 7, 6, 3, 2, 1 18, 19, 22, 23, 24, 25, 28, 29, 30 98 85 93 95 96 97 86 64 89, 88 15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 38, 43, 87 14, 16, 31, 39, 42, 66, 84, 92, 94
Synchronous Data Input / Output
Synchronous Chip Select Synchronous Byte Write Enable Synchronous Byte "a" Write Enable Synchronous Byte "b" Write Enable Synchronous Byte "c" Write Enable Synchronous Byte "d" Write Enable Asynchronous Output Enable Asynchronous Sleep Mode Main Clock Input Core Power Supply Ground Output Buffer Power Supply Output Buffer Ground Input Reference No Connection
K, /K VDD VSS VDDQ VSSQ VREF NC
Notes 1. If Byte Write Operation is not used, Byte Write Pins (/SBa, /SBb, /SBc, /SBd) are to be tied to VSS. 2. If Sleep Mode is not used, ZZ Pin is to be tied to VSS.
Remark This device only supports Single Differential Clock, R / R Mode. (R / R stands for Registered Input / Registered Output.)
Preliminary Data Sheet M14440EJ1V0DS
3
PD4483362
Late Write Block Diagram
18 SA0 to SA17 K /K /SS K /K /SS Write clock generator Address register Write address register Mux
/SW
/SW
/SBa
/SBa Write control logic
Memory cell array 9,437,184 bits Read comp. Data Data in out
/SBb
/SBb
/SBc
/SBc
/SBd
/SBd
Mux
DQa1 to DQa9 DQb1 to DQb9 DQc1 to DQc9 DQd1 to DQd9
36 Data in register
Output Register
/G
/G
ZZ
ZZ
4
Preliminary Data Sheet M14440EJ1V0DS
PD4483362
Synchronous Truth Table
ZZ L L L L L L H /SS H L L L L L x /SW x H L L L L x /SBa x x L L H H x /SBb x x L H L H x /SBc x x L H L H x /SBd x x L H L H x Mode Not selected Read Write Write Write Abort Write Sleep Mode DQa1-9 DQb1-9 DQc1-9 DQd1-9 Hi-Z Dout Din Din Hi-Z Hi-Z Hi-Z Hi-Z Dout Din Hi-Z Din Hi-Z Hi-Z Hi-Z Dout Din Hi-Z Din Hi-Z Hi-Z Hi-Z Dout Din Hi-Z Din Hi-Z Hi-Z Power Active Active Active Active Active Active Standby
Remark x : Don't care
Output Enable Truth Table
Mode Read Read Sleep (ZZ=H) Write (/SW=L) Deselect (/SS=H) /G L H x x x DQ Dout Hi-Z Hi-Z Hi-Z, Din Hi-Z
Remark x : Don't care
Preliminary Data Sheet M14440EJ1V0DS
5
PD4483362
Electrical Specifications
Absolute Maximum Ratings
Parameter Supply voltage Output supply voltage Input voltage Input / Output voltage Operating temperature Storage temperature Symbol VDD VDDQ VIN VI/O TA Tstg Condition MIN. -0.5 -0.5 -0.5 -0.5 0 -55 TYP. MAX. +4.0 +4.0 VDD+0.3 VDDQ+0.3 50 +125 Unit V V V V C C Note 1 1 1 1
Note 1. -2.0 V MIN. (Pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to 50 C)
Parameter Core supply voltage Output buffer supply voltage Input reference voltage Low level input voltage High level input voltage Symbol VDD VDDQ VREF VIL VIH Conditions MIN. 3.135 1.4 0.7 -0.3
Note
TYP. 3.3 1.5 0.75
MAX. 3.465 1.6 0.8 VREF-0.1 VDDQ+0.3
Unit V V V V V
VREF+0.1
Note -0.8 V MIN. (Pulse width : 2 ns) Recommended AC Operating Conditions (TA = 0 to 50 C)
Parameter Input reference voltage Low level input voltage High level input voltage Symbol VREF (RMS) VIL VIH Conditions MIN. -5% -0.3 VREF+0.2 TYP. MAX. +5% VREF-0.2 VDDQ+0.3 Unit V V V
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Note Input capacitance Input / Output capacitance Clock Input Capacitance Symbol CIN CI/O Cclk VIN = 0 V VI/O = 0 V Vclk = 0 V Test conditions MAX. 5.5 7.0 6.0 Unit pF pF pF
Note These parameters are not 100% tested.
6
Preliminary Data Sheet M14440EJ1V0DS
PD4483362
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Input leakage current DQ leakage current Operating supply current Symbol ILI ILO IDD Conditions VIN = 0 to VDD VI/O = 0 to VDDQ VIN = VIH or VIL, /SS = VIL, ZZ = VIL, Cycle = MAX., IDQ = 0 mA Sleep mode power supply current ISBZZ ZZ = VIH, All other inputs = VIH or VIL, Cycle = DC, IDQ = 0 mA 20 mA MIN. -5 -5 TYP. MAX. +5 +5 350 Unit
A A
mA
Output Voltage on Push-Pull Output Buffer Mode
Parameter Low level output voltage High level output voltage Symbol VOL VOH IOL = +2 mA IOH = -2 mA Conditions MIN. - VDDQ-0.3 TYP. MAX. 0.3 - Unit V V
Preliminary Data Sheet M14440EJ1V0DS
7
PD4483362
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
Input waveform (rise and fall time = 0.5 ns (20 to 80%))
1.25 V VDDQ / 2 0.25 V Test Points VDDQ / 2
Output waveform
VDDQ / 2
Test Points
VDDQ / 2
8
Preliminary Data Sheet M14440EJ1V0DS
PD4483362
Single Differential Clock, Registered Input / Registered Output Mode
Parameter Symbol -A75 (133 MHz) MIN. Clock cycle time Clock phase time tKHKH tKHKL / tKLKH Setup times Address Write data Write enable Chip select Hold times Address Write data Write enable Chip select Clock access time K high to Q change /G low to Q valid /G low to Q change /G high to Q Hi-Z K high to Q Hi-Z (/SW) K high to Q Hi-Z (/SS) K high to Q Lo-Z Sleep Mode Recovery Sleep Mode Enable tAVKH tDVKH tWVKH tSVKH tKHAX tKHDX tKHWX tKHSX tKHQV tKHQX tGLQV tGLQX tGHQZ tKHQZ tKHQZ2 tKHQX2 tZZR tZZE - 1.5 - 0 0 1.5 1.5 1.5 - - 3.8 - 3.8 - 3.8 3.8 3.8 - 7.5 7.5 ns ns ns ns ns ns ns ns ns ns 1 2 1 2 2 2 2 2 0.5 - ns 1.5 - ns 7.5 2.0 MAX. - - ns ns Unit Notes
Notes 1. See figure. (VTT = 0.75 V)
VTT 50
ZO = 50 DQ (Output)
20 pF
2. See figure. (VTT = 0.75 V)
VTT 50 DQ (Output) 5 pF
Preliminary Data Sheet M14440EJ1V0DS
9
10
tKHAX tKHKH tKHKL tKLKH tAVKH b f g h tKHSX tSVKH c d e i j k tKHWX tWVKH tGLQX tGHQZ tGLQV Qe Qf Qg tKHQZ2 tKHQX2 Qa Qb tKHQX tKHQV Qc Qi
Read Operation
/K
K
Address
a
/SS
Preliminary Data Sheet M14440EJ1V0DS
/SW
/G
DQ
PD4483362
Write Operation
/K tKHAX tKHKH tKHKL tKLKH tAVKH m tKHSX tSVKH n o p q r s t u v
K
Address
l
/SS tKHWX tWVKH
/SW tKHWX tWVKH
Preliminary Data Sheet M14440EJ1V0DS
/SBx
/G tGLQX tGHQZ Ql tDVKH tKHDX Dn tGLQV Qo Qp Qq tKHQZ Ds tKHQX2 Qt
DQ
PD4483362
11
12
c d e f g h i j k l tZZE tZZR Qa Qb Qc Qj
Sleep Mode
/K
K
Address
a
b
/SS
Preliminary Data Sheet M14440EJ1V0DS
/SW
/ZZ
DQ
PD4483362
PD4483362
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A B
80 81
51 50
detail of lead end S C D R Q
100 1
31 30
F G H I
M
J
K P S
N
S
L M
NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 22.00.2 20.00.2 14.00.2 16.00.2 0.825 0.575 0.32 +0.08 -0.07 0.13 0.65 (T.P.) 1.00.2 0.50.2 0.17 +0.06 -0.05 0.10 1.4 0.1250.075 3 +7 -3 1.7 MAX. S100GF-65-8ET-1
Preliminary Data Sheet M14440EJ1V0DS
13
PD4483362
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the PD4483362.
Type of Surface Mount Device
PD4483362GF: 100-pin PLASTIC LQFP (14 x 20)
14
Preliminary Data Sheet M14440EJ1V0DS
PD4483362
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Preliminary Data Sheet M14440EJ1V0DS
15
PD4483362
* The information in this document is current as of April, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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